Portfolio

Electronic Voting Machine

Published:

Designed an electronic voting machine using Proteus software that utilizes voter verification. This project aimed to address the issue of voter fraud and ensure that only eligible voters are able to cast their ballots.

MFCC Audio Feature Extraction Accelerator

Published:

Designed a fixed-point DSP hardware accelerator for MFCC extraction, implementing pre-emphasis, framing/windowing, 512-point FFT, Mel filterbanks, log scaling, DCT, and liftering in Verilog. Achieved <1% numerical error vs. MATLAB reference with ∼7.7µs latency per frame, enabling real-time speech processing for low-power IoT devices.